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Solid State Imaging Sensors - Frame Transfer Image Sensor, Interline Transfer CCD Image Sensor, CMOS, Buried Photodiode Image Sensor

silicon type light layer

Digital Imaging Consultant

Frame Transfer Image Sensor

The Frame Transfer image sensor is revealed in Figure 11a and is the least complicated of this group. The substrate is p-type 1 silicon where the potential well is formed (p-Well) to hold the generated and captured photoelectrons. An epitaxial layer of n-type 2 silicon is grown above the p-Well, which isolates the captured photoelectrons from the insulating SiO 2 layer. On top of the insulating layer, four transparent conducting electrodes are fabricated to control the transfer of the captured electrons from the body of the sensor to a horizontal CCD that leads to the output amplifier circuitry. The transparent electrodes are either poly-silicon or indium tin oxide. The indium tin oxide electrodes are preferable because they have much less absorption of blue light than the poly-silicon electrodes. The thin n-type layer separates the electrons to be transferred from the boundary between the substrate and the interface with the insulator, resulting in a Buried Channel FT CCD. The four phases refers to the number of transfers required to move the charge from one pixel to the adjacent pixel. It should be noted that during exposure, while the entire pixel can generate photoelectrons, they are collected in a potential well that resides below only one or two of the four transparent electrodes.

1 p-type silicon consists of silicon doped with a relatively small percentage of material that has only three valence electrons, such as indium. Because a silicon atom has four valence electrons, which form covalent bonds with other valence electrons from other silicon atoms, an interstitial indium atom leaves the local region with an unbalanced number of electrons. This looks like a positive “hole.” Because the positive charge can pair with an electron, it is call an acceptor.

2 n-type silicon consists of silicon doped with a relatively small percentage of atoms that have five valence electrons, such as antinomy, which has one more than silicon. This excess electron is then able to move about in the crystal and is hence called a donor.

Interline Transfer CCD Image Sensor

The Interline Transfer CCD image sensor is shown in Figure 11b. Here the substrate is n-type silicon with a p-Well region grown above it. Within the p-Well structure, n-type silicon and p +—type silicon (higher concentration of holes or acceptor atoms than the p-Well material) are used to form a photo-diode, a charge transfer gate, and a vertical CCD shift register. The electrodes to control the gate and vertical CCD shift register are made of a transparent conductor such as poly-silicon. SiO 2 is used as the insulating layer. The insulator above the photo-diode is coated with an anti-reflection layer to increase the effective quantum efficiency of the photo-diode. Since the vertical CCD shift register must not capture photoelectrons (other than those captured by the photo-diode) an opaque metal mask is added to all part surfaces of the sensor other than the opening to the photo-diode. The charges collected by the photo-diodes are all transferred at the same time to the vertical shift registers by means of the transistor gate. Small p-type regions are placed at each end of the pixel to prevent electrons generated under one pixel to diffuse to an adjacent pixel during exposure; these are called channel blocks. Similar implants can be used to shunt excess photoelectrons (those that exceed the potential well capacity of the photo-diode) into the substrate and are called overflow drains. The actual imaging area of the Interline Transfer CCD, as defined by the fill factor, is considerably less than that of the Frame Transfer CCD.


A typical CMOS imaging sensor is shown in Figure 11c. CMOS stands for complementary metal oxide semiconductor. A p type silicon layer is built upon another p type silicon layer. A pinned photodiode is fabricated within the p-layer by using a p+ and n type silicon. A p-well is fabricated to the right of the pinned photodiode along with two Field Effect transistors, formed by n+ silicon imbedded in the p-well and controlled by two metal electrodes on the surface of the pixel. Just as with the Interline CCD, only a fraction of the surface area of the CMOS sensor is used to capture light. The pinned photodiode limits the total charge capacity of the sensor (as opposed to the photodiode in Figure 11b). During the exposure cycle, charge is collected in the depletion region of the pinned photodiode. The gate electrode is then used to lower the potential barrier to the charge and allows it to flow into the p-well regions, where it is isolated by returning the transfer gate electrodes to their normal voltage. The second FET is then used to transfer the charge stored in the p-well to an output amplifier by means of sensor lines that have been fabricated on the sensor. There are addressed FETs that enable individual columns and rows, or pixels, fabricated on the chip, but they are not shown in the diagram. The advantage of the CMOS sensor is that all the control circuits can be fabricated on the imaging chip, while this is not possible for the two CCD samples above. Another disadvantage, besides the low fill factor, is that the three to four transistors per pixel will introduce more noise, as will the capacitance of the sensor lines.

The fill factor of both the Interline and CMOS sensors is much less than that of the Frame Transfer CCD sensors. To compensate for the “wasted” light, an array of micro-lenses is fabricated on top of the two sensors. The micro-lenses can increased the captured light up to a factor of three and are used on most IT and CMOS sensors. Color encoding is achieved by placing a Color Filter Array (CFA) between the micro-lens array and the actual sensor.

Buried Photodiode Image Sensor

Figure 11d shows a 3-D Buried Photodiode sensor. A series of photodiodes are formed at the p-n junction, as shown in the diagram. Silicon has a very large change in absorption light over the visible spectrum. There is a ratio of more than 100:1 from blue to red light, with blue light being more highly absorbed. Hence silicon forms a natural filter for encoding color. The blue light is absorbed near the first n-p interface, green light near the next p-n interface and, finally, red light is absorbed deep within the sensor at the next n-p interface. The stored charge is read out by means of circuitry not shown in the diagram. The greatest advantage of the 3-D Buried Photodiode sensor is that the sampling for each color is the same and the much less than any sensor with a CFA. This results in much less aliasing and color artifacts. 3 There is an additional advantage in that the resulting spectral sensitivities are closer to that of the human visual system, thus allowing for potential superior color reproduction. Since the readout circuitry takes up valuable surface area on the chip, 3-D Buried Photodiode sensors also use micro-lens arrays to improve the effective quantum efficiency.

3 Color aliasing arises from sub-sampled images. When an image is sub-sampled, any frequency content that is above half the sampling frequency (the Nyquist Frequency) will appear as low-frequency information or an aliased signal. When a CFA is used to encode the color data, the three channels are physically out of phase and thus the banding takes on strongly colored edges.

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