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LCD Display Interfaces

controller buffer panels controllers

Definition: The LCD display controller provides an interface between the multimedia processor and a flat-panel display module.

The controller can be integrated as a part of system on chip or can be discrete. The image rendered by the application is displayed on the screen for the user by the LCD controller. The image of the screen on the memory is called the frame buffer. The configuration of the controller is typically established through programmable options for display type, resolution, pixel depth, overlays, hardware cursor, and output data formatting.

LCD panels can be passive (Dual scan STN or regular STN) or active (based on TFT-Thin Film Transistors). Active matrix panels are power efficient and have higher density as well as higher retention capability. There are some panels which incorporate the display buffer with the panel, allowing the controller to refresh the buffer at the content update rate as opposed to refresh rate specified for the panel. Display resolution varies based on the platform. QVGA and VGA (640×480) sized panels are becoming common in the hand-held space. Typical controllers today support resolution up to 800×600. Typical panels support 2, 4, 8,16, 18 19, 24 and 25 bits per pixel (bpp) (referred to as Pixel depth) are used with RGB and RGBT formats. The RGBT format uses the most significant bit to indicate transparency for overlay support. For bit depths less than 8 bpp, there are three separate 256×25-bit palette RAMs that can be used to map the 2,4, or 8bpp values to 16- or 25-bit values. The display buffer is organized as, a base plane and a set of overlays. Overlay represent display content which is superposed (or blended) on the base-plane. Overlays ease the software burden of sharing the display buffer between different system components while displaying multiple display objects simultaneously (e.g. an overlay is used to display camera image or the cursor on the screen where as the base plane displays the desktop).

LCD controllers typically have a set of DMA engines to read data from the display buffer for the base plane and overlays. Logic is provided to ensure overlay and the base planes are superposed in the desired fashion. The controller also has a set of FIFOs to manage the flow rate difference at the display interface and memory interface. Advanced integrated controllers also suport different color formats such as YUV, YCbCr (444, 422, 420) color formats, so that the controller works efficiently with both video playback and video preview from a CMOS or CCD image sensor. Since the display panels accept only RGB format, the controllers support color space conversion (YUV to RGB conversion based on the CCIR 601-2 standard). Display buffer for YCbCr can be organized as planner format (Y, Cb and Cr can occupy different memory regions) or packed (Y, Cb, Cr data values interleave). Also for effective combination of different display planes, dithering engine is introduced. LCD controllers also optionally support double buffering so that application can render next frame while the controller displays the current one. Figure 1 shows a block diagram of a typical LCD controller as used in the PXA27× processor.

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